1. Field of the Invention
The present invention relates to a semiconductor device including an LDMOSFET (Lateral Double diffused Metal Oxide Semiconductor Field-Effect Transistor).
2. Description of Related Art
An LDMOSFET employing a resurf structure is generally known as a MOSFET having a high withstand voltage.
FIG. 7 is a schematic sectional view of a semiconductor device 101 including an LDMOSFET employing a resurf structure.
A thick-film SOI (Silicon On Insulator) substrate 102 forming the base of the semiconductor device 101 has a structure formed by stacking an N-type epitaxial layer 105 made of Si (silicon) on a P-type silicon substrate 103 through a BOX (Buried Oxide) layer 104 made of SiO2 (silicon oxide).
An annular deep trench 106 is dug in the epitaxial layer 105 from the surface thereof. The deepest portion of the deep trench 106 reaches the BOX layer 104. The deep trench 106 is filled up with polysilicon 108 through a silicon oxide film 107. Thus, the region surrounded by the deep trench 106 provides an element forming region isolated (dielectrically insulated) from the periphery thereof so that the LDMOSFET is formed thereon.
In the element forming region, a P-type drain buffer region 109 is formed in a surface layer portion of the epitaxial layer 105. A P-type drain contact region 110 having a higher P-type impurity concentration than that of the drain buffer region 109 is selectively formed in a surface layer portion of the drain buffer region 109.
A P-type drift region 111 is formed around the drain buffer region 109. The drift region 111 is in contact with the drain buffer region 109. A LOCOS oxide film 112 is formed on the overall drift region 111.
In the surface layer portion of the epitaxial layer 105, an N-type body region 113 is formed between the deep trench 106 and the drift region 111 at intervals therefrom. A P-type source region 114 and an N-type body contact region 115 having a higher N-type impurity concentration than that of the body region 113 are formed in a surface layer portion of the body region 113 adjacently to each other.
On the surface of the epitaxial layer 105, a gate oxide film 116 is formed between the source region 114 and the LOCOS oxide film 112. A gate electrode 117 is formed on the gate oxide film 116.
The thick-film SOI substrate 102 is covered with an interlayer dielectric film 118 made of SiO2. A source wire 119 and a drain wire 120 are formed on the interlayer dielectric film 118. The source wire 119 is connected to the source region 114 and the body contact region 115 through a contact hole 121 formed in the interlayer dielectric film 118. The drain wire 120 is connected to the drain contact region 110 through another contact hole 122 formed in the interlayer dielectric film 118.
In this semiconductor device 101, an N-type high-concentration buried region 123 having a higher N-type impurity concentration (1E18 to 1E20/cm3, for example) than that of the epitaxial layer 105 is formed in the epitaxial layer 105 under the body region 113. The high-concentration buried region 123 has the same shape as the body region 113 in plan view.
When the source wire 119 is grounded and a negative voltage is applied to the drain wire 120, a depletion layer spreads from the boundary between the epitaxial layer 105 and the drift region 111. In the structure shown in FIG. 7, the high-concentration buried region 123 is so formed under the body region 113 that the depletion layer can be inhibited from extending in the lateral direction (direction orthogonal to the depth direction), whereby improvement of the withstand voltage can be expected.
If the negative voltage applied to the drain wire 120 is increased, however, a potential distribution shown in FIG. 8 is caused in the epitaxial layer 105 due to the low impurity concentration of the epitaxial layer 105, and the depletion layer passes under the high-concentration buried region 123 and extends toward the source region 114 through the portion between the high-concentration buried region 123 and the deep trench 106. In the structure (having the high-concentration buried region 123) shown in FIG. 7, therefore, increase of the withstand voltage of the LDMOSFET is limited.